Uma técnica de polarização para um comparador de corrente CMOS

Abstract

In this work a technique to bias a CMOS current comparator is presented. The current comparator circuit uses the flipped voltage follower (FVF) block as input stage, and a cascode structure is proposed to bias properly this stage. Alternatives to bias the input block are presented, demonstrating the trade-off between the response time and the input impedance of the circuit. The circuit was developed using the CMOS technology of the Taiwan Semiconductor Manufacturing Company (TSMC) 0.18 μm process. The postlayout simulation results show that the current comparator, with the proposed structure to bias the input stage, exhibits a propagation time of 7.5 ns with a power consumption of 47 μW when the input is a pulsed current amplitude ±2 μA with a frequency of 50 MHz. The input impedance value is 50 Ω at the operating frequency. The minimum current, at low frequencies, that the circuit can detect is 200 pA. The cascode structure, proposed to bias the FVF block, provides a voltage value of 1.01 V with a coefficient of variation of ±0.001%. The results of the characterization of the manufactured prototype confirm that the current comparator, with the proposed technique to bias the input circuit, is appropriate and functional.