Sistema fuzzy tipo-2 intervalar implementado em FPGA baseado no algoritmo de Nie-Tan

Abstract

This work aims to propose and validate an architecture of an interval type-2 fuzzy logic systems implemented in FPGA, which meets real-time control applications, with serial processing in the inference mechanisms. This work presents the design and implementation of the circuits that make up the interval type-2 fuzzy logic systems, such as: the type-2 interval fuzzifier circuit (FOU); the minimum and maximum circuits that are used in the Mamdani inference mechanism (type-2); the circuit applied to the state machine that is used by the rules base and the circuit that processes the reducer-type and defuzzification operations based on the Nie-Tan algorithm. The hardware presented has two 8-bit inputs with four Gaussian pertinence functions for each input, sixteen rules, and an 8-bit output with seven pertinence functions. Finally, the results of the FPGA implementation are validated using the same interval type-2 fuzzy logic systems implemented in Matlab® with a Toolbox for type-2 fuzzy