Resumo:
The interest in Quasi Delay Insensitive digital circuits, especially Null Convention Logic
circuits, stems from the absence of a need for a global clock signal to control the circuit’s
parts. This results in faster, energy-efficient, and more robust circuits. With the
increasing demand for this type of circuit in the industry, undesirable modifications from
malicious actors are a concern, given that the large-scale production process for these
circuits is divided among various companies and collaborators, which makes it difficult to
have complete knowledge of its entire production process. Given this context, this work
aims to study and analyze the Probabilistic Transitions method applied to combinational
Null Convention Logic circuits. The algorithm receives information about the interconnections
of the original and modified circuits and compares, based on the values of each
logic element, whether or not modifications occurred between the circuits, using the valid
input value cases (“01” and “10”). Based on the discussions contained in this work, the
following results are presented: functional descriptions and simulations of the test circuits;
the implementation of a transpiler to convert Quartus software output files into the
algorithm’s required netlist format; and the development of the probabilistic transition
algorithm itself. The algorithm operates in two modes: when provided with a single netlist,
it calculates transition values for all elements to generate a unique circuit signature; when
provided with two netlists, the program performs individual calculations and executes a
comparative analysis, reporting potential divergences and their specific locations.
