Abstract:
This work presents a topology of a voltage and current reference with little sensitivity in
relation to operating temperature, supply voltage and the effects of CMOS fabrication
processes. To achieve thermal compensation, a self-cascode composite transistor (SCCT)
configuration is used, which is responsible for the generation of PTAT (proportional to absolute
temperature) and CTAT (complementary to absolute temperature) voltages, which are summed
through the aid of amplifiers operational (AmpOp) and current mirrors.
The circuit provides an average voltage and current reference, measured values, of 483.58
mV and 1.317 µA with temperature coefficients (TC) of 25 ppm/°C and 77 ppm/°C
respectively, operating in a temperature range from -30 °C to 100 °C, with a minimum voltage
of 850 mV and average PSR at 50 Hz, -15.2 dB and -16.36 dB at 1.8 V for VREF and IREF
respectively. The developed circuit area is 269 µm x 654 µm.
It is presented in this dissertation, the project description, and pertinent simulations of the
post-layout circuit of the proposed topology and its electrical characterization. The circuit was
developed using a standard 180 nm CMOS process.
