Resumo:
The term low voltage was initially used for digital and analog CMOS circuits
working under 3V, on processes that used to work on a 5V power supply. When considering
the market trend towards low-voltage and low-power, the frequency response, the power
supply voltage and consumption are the main specifications of the analog circuit design.
Unfortunately, the main limitation on low-voltage circuits is the threshold voltage. Since the
threshold voltage does not reduce satisfactorily, there is a need of new architectures that
minimize its effect.
This work describes a new and simple rail-to-rail Miller OTA architecture for
ultra low-voltage and ultra low-power. The topology uses bulk-driven differential pair and DC
voltage shifters. It is presented a methodology for the extraction of DC parameters from
BSIM3v3 model that was used in the development of this new amplifier topology. It is also
presented a methodology for the design of the circuit that optimizes the output signal transient
behavior, according to the small signal AC model. Since all transistors work on weak
inversion, the presented topology is capable of running on a 600mV power supply voltage and
a power consumption of just 550nW, for a standard 0.35 m CMOS TSMC process.
